题目：SECDA: Efficient Hardware/Software Co-Design of FPGA -based DNN Accelerators for Edge Inference. 名称：SECDA：用于边缘推理的基于 FPGA 的 DNN 加速器的高效硬件/软件协同设计. 论文： arxiv.org/abs/2110.0047. 代码： github.com/gicLAB/SECDA. 题目：PREBA: A Hardware/Software Co-Design for Multi-Instance GPU based AI Inference. Provide a Template Resource Optimization search algorithm to co-optimize the accelerator architecture and scheduling. vDNN: Virtualized Deep Neural Networks for Scalable, Memory-Efficient Neural Network Design. This paper presents a detailed design space exploration (DSE) of technology-system co-design for systolic-array accelerators. We focus on practical/mature on-chip memory technologies, including SRAM, eDRAM, MRAM, and 3D vertical RRAM (VRRAM). It develops a novel solution to the dataflow optimization problem for CNN accelerators by formulating and solving a constrained nonlinear (DGP - Disciplined Geometric Programming) optimization problem that is solved by an off-the-shelf convex solver (CVXPY) Community Education Westborough, , , , , , , 0, The Geeky Guide to Nearly Everything: [TV] Community: Season 4, www.geeky-guide.com, 0 x 0, jpg, 题目：SECDA: Efficient Hardware/Software Co-Design of FPGA -based DNN Accelerators for Edge Inference. 名称：SECDA：用于边缘推理的基于 FPGA 的 DNN 加速器的高效硬件/软件协同设计. 论文： arxiv.org/abs/2110.0047. 代码： github.com/gicLAB/SECDA. 题目：PREBA: A Hardware/Software Co-Design for Multi-Instance GPU based AI Inference. Provide a Template Resource Optimization search algorithm to co-optimize the accelerator architecture and scheduling. vDNN: Virtualized Deep Neural Networks for Scalable, Memory-Efficient Neural Network Design. This paper presents a detailed design space exploration (DSE) of technology-system co-design for systolic-array accelerators. We focus on practical/mature on-chip memory technologies, including SRAM, eDRAM, MRAM, and 3D vertical RRAM (VRRAM). It develops a novel solution to the dataflow optimization problem for CNN accelerators by formulating and solving a constrained nonlinear (DGP - Disciplined Geometric Programming) optimization problem that is solved by an off-the-shelf convex solver (CVXPY), 20, community-education-westborough, Education Zone

We propose Adyna, a novel hardware-software co-design solution to eficiently support DynNN inference. Adyna uses a unified representation to capture most existing DynNNs to enable a general... This capability is enabled by a novel three-phase co-design framework, with the following new features: (a) decoupling DNN training from the design space exploration of hardware architecture and neural architecture, (b) providing a hardware-friendly neural architecture space by considering hardware characteristics in constructing the search ... We discuss various architectures that support DNN executions in terms of computing units, dataflow optimization, targeted network topologies, architectures on emerging technologies, and accelerators for emerging applications. We also provide our visions on the future trend of AI chip designs.

This capability is enabled by a novel three-phase co-design framework, with the following new features: (a) decoupling DNN training from the design space exploration of hardware architecture and neural architecture, (b) providing a hardware-friendly neural architecture space by considering hardware characteristics in constructing the search ... We discuss various architectures that support DNN executions in terms of computing units, dataflow optimization, targeted network topologies, architectures on emerging technologies, and accelerators for emerging applications. We also provide our visions on the future trend of AI chip designs. The designs of deep neural network (DNN) accelerators have gradually gained attention due to the increased demand for real-time AI applications. On the other ha ntly while neglecting the vast yet crucial joint effect of layer fusion. To address this shortcoming, we propose CASCO, a cascaded and holistic co-optimization aware of all co-design aspects, including the accelerator’s hardware archit In this paper, we propose a complete hardware-software co-design framework to support irregular sparse model. Specifically, we prune redundant model weights through iterative pruning by increasing the penalty factor and improve the hardware efficiency through hardware threads control.

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